dc.relation.references | ABDUL, J. J. M.; ALWAN, M. A.; AL-EBADI, M. A new hardware architecture for parallel shortest path searching processor based-on fpga technology. Int. J. Electron. Comput. Sci. Eng, v. 1, p. 2572–2582, 2012. Citado nas páginas 42 e 93.
ATAY, N.; BAYAZIT, B. A motion planning processor on reconfigurable hardware. In: IEEE. Proceedings 2006 IEEE International Conference on Robotics and Automation, 2006. ICRA 2006. [S.l.], 2006. p. 125–132. Citado nas páginas 39 e 41.
BADR, E. M.; MOUSSA, M. I. An upper bound of radio k-coloring problem and its integer linear programming model. Wireless Networks, Springer, v. 26, p. 4955–4964, 2020. Citado na página 42.
BERRETTINI, E.; D’ANGELO, G.; DELLING, D. Arc-flags in dynamic graphs. In: SCHLOSS DAGSTUHL-LEIBNIZ-ZENTRUM FÜR INFORMATIK. 9th Workshop on Algorithmic Approaches for Transportation Modeling, Optimization, and Systems (ATMOS’09). [S.l.], 2009. Citado na página 46.
BHASKER, J.; CHADHA, R. Static timing analysis for nanometer designs: a practicalapproach. [S.l.]: Springer Science & Business Media, 2009. Citado nas páginas 12, 108, 109 e 110.
BLACK, P. E. Dictionary of algorithms and data structures. Paul E. Black, 1998.página 35. Citado na BULUÇ, A.; GILBERT, J. R.; BUDAK, C. Solving path problems on the gpu. Parallel Computing, Elsevier, v. 36, n. 5-6, p. 241–253, 2010. Citado na página 42.
CABODI, G.; CAMURATI, P.; GARBO, A.; GIORELLI, M.; QUER, S.; SAVARESE, F. A smart many-core implementation of a motion planning framework along a reference path forautonomous cars. Electronics, MDPI, v. 8, n. 2, p. 177, 2019. Citado nas páginas 38 e 41.
CHI, Y.; GUO, L.; CONG, J. Accelerating sssp for power-law graphs. p. 190–200, 2022.na página 52. Citado
CHIRILA, M.; D’ALBERTO, P.; TING, H.-Y.; VEIDENBAUM, A.; NICOLAU, A. A heterogeneous solution to the all-pairs shortest path problem using fpgas. In: IEEE. 2022 23rd
International Symposium on Quality Electronic Design (ISQED). [S.l.], 2022. p. 108–113.Citado nas páginas 42 e 93.
CONG, J.; FANG, Z.; LO, M.; WANG, H.; XU, J.; ZHANG, S. Understanding performance differences of fpgas and gpus. In: IEEE. 2018 IEEE 26th Annual International Symposium on
Field-Programmable Custom Computing Machines (FCCM). [S.l.], 2018. p. 93–96. Citado na página 51.
CORMEN, T. H.; LEISERSON, C. E.; RIVEST, R. L.; STEIN, C. Introduction to algorithms.[S.l.]: MIT press, 2009. Citado nas páginas 10, 27 e 28.
CRAUSER, A.; MEHLHORN, K.; MEYER, U.; SANDERS, P. A parallelization of dijkstra’s shortest path algorithm. In: SPRINGER. International Symposium on MathematicalFoundations of Computer Science. [S.l.], 1998. Citado nas páginas 47, 49, 52, 53, 54 e 66.
DEO, N. Graph theory with applications to engineering and computer science. [S.l.]: CourierDover Publications, 2017. Citado nas páginas 10, 25, 26 e 30.
DIJKSTRA, E. W. et al. A note on two problems in connexion with graphs. Numerische mathematik, v. 1, n. 1, 1959. Citado na página 31.
DRISCOLL, J. R.; GABOW, H. N.; SHRAIRMAN, R.; TARJAN, R. E. Relaxed heaps: An alternative to fibonacci heaps with applications to parallel computation. Communications of the ACM, ACM New York, NY, USA, v. 31, n. 11, 1988. Citado na página 48.
EDMONDS, N.; BREUER, A.; GREGOR, D. P.; LUMSDAINE, A. Single-source shortest paths with the parallel boost graph library. In: The Shortest Path Problem. [S.l.: s.n.], 2006. Citadonas páginas 48, 49 e 52.
FERNANDEZ, I.; CASTILLO, J.; PEDRAZA, C.; SANCHEZ, C.; MARTINEZ, J. I. Parallel implementation of the shortest path algorithm on fpga. In: IEEE. 2008 4th Southern Conference on Programmable Logic. [S.l.], 2008. p. 245–248. Citado na página 93.
FRANCIS, A.; FAUST, A.; CHIANG, H.-T. L.; HSU, J.; KEW, J. C.; FISER, M.; LEE, T.-W. E. Long-range indoor navigation with prm-rl. IEEE Transactions on Robotics, IEEE, v. 36, n. 4, p. 1115–1134, 2020. Citado na página 40.
GOLDBERG, A. V. Point-to-point shortest path algorithms with preprocessing. In: SPRINGER. International Conference on Current Trends in Theory and Practice of Computer Science. [S.l.], 2007. p. 88–102. Citado na página 46.
GUO, L.; LAU, J.; RUAN, Z.; WEI, P.; CONG, J. Hardware acceleration of long read pairwise overlapping in genome sequencing: A race between fpga and gpu. In: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). [S.l.: s.n.], 2019. p. 127–135. ISSN 2576-2621. Citado na página 51.
HARISH, P.; NARAYANAN, P. J. Accelerating large graph algorithms on the gpu using cuda. In: SPRINGER. International conference on high-performance computing. [S.l.], 2007. p. 197–208. Citado na página 42.
HART, P. E.; NILSSON, N. J.; RAPHAEL, B. A formal basis for the heuristic determination of minimum cost paths. IEEE transactions on Systems Science and Cybernetics, IEEE, v. 4, n. 2, 1968. Citado na página 34.
HORTELANO, J. L.; TRENTIN, V.; ARTUÑEDO, A.; VILLAGRA, J. Gpu-accelerated interaction-aware motion prediction. Electronics, MDPI, v. 12, n. 18, p. 3751, 2023. Citado naspáginas 39 e 41.
HUANG, L.; GONG, Y.; SUI, Y.; ZANG, X.; YUAN, B. Moped: Efficient motion planning engine with flexible dimension support. In: IEEE. 2024 IEEE International Symposium on
High-Performance Computer Architecture (HPCA). [S.l.], 2024. p. 483–497. Citado na página 93.
JASIKA, N.; ALISPAHIC, N.; ELMA, A.; ILVANA, K.; ELMA, L.; NOSOVIC, N. Dijkstra’s shortest path algorithm serial and parallel execution performance analysis. In: IEEE. 2012 proceedings of the 35th international convention MIPRO. [S.l.], 2012. p. 1811–1815. Citado na página 42.
KAVRAKI PETR SVESTKA, J.-C. L. L. E.; OVERMARS, M. H. Probabilistic roadmaps for path planning in high-dimensional configuration spaces. IEEE Transactions on Robotics and Automation, v. 12, 1996. Citado na página 30.
KLANCAR, G.; ZDESAR, A.; BLAZIC, S.; SKRJANC, I. Wheeled mobile robotics: from fundamentals towards autonomous systems. [S.l.]: Butterworth-Heinemann, 2017. Citadonas páginas 10, 24, 25, 29, 30, 31, 35, 36 e 37.
LAVALLE, S. M. Planning algorithms. [S.l.]: Cambridge university press, 2006. Citado naspáginas 10, 29 e 30.
LEE, K. D.; HUBBARD, S. Data Structures and Algorithms with Python. [S.l.]: Springer, 2015. Citado na página 33.
LEI, G.; DOU, Y.; LI, R.; XIA, F. An fpga implementation for solving the large single-source- shortest-path problem. IEEE Transactions on Circuits and Systems II: Express Briefs, IEEE, v. 63, n. 5, 2015. Citado na página 49.
LIU, J.; XIAO, G.; WU, F.; LIAO, X.; LI, K. Aapp: An accelerative and adaptive path plannerfor robots on gpu. IEEE Transactions on Computers, IEEE, 2023. Citado nas páginas 38 e 41.
LIU, S.; WAN, Z.; YU, B.; WANG, Y. Planning on fpgas. In: Robotic Computing on FPGAs. [S.l.]: Springer, 2021. p. 91–108. Citado na página 38.
MEHLHORN, K. Data structures and algorithms 2: graph algorithms and NP-completeness.[S.l.]: Springer Science & Business Media, 2012. v. 2. Citado nas páginas 26, 27 e 28.
MEHTA, A. B. Uvm (universal verification methodology). ASIC/SoC Functional Design
Verification: A Comprehensive Guide to Technologies and Methodologies, Springer, p. 17–64, 2018. Citado na página 106.
MURRAY, S.; FLOYD-JONES, W.; QI, Y.; KONIDARIS, G.; SORIN, D. J. The microarchitecture of a real-time robot motion planning accelerator. In: IEEE. 2016 49th Annual IEEE/ACMInternational Symposium on Microarchitecture (MICRO). [S.l.], 2016. Citado nas páginas 10, 14, 39, 40 e 41.
MURRAY, S.; FLOYD-JONES, W.; QI, Y.; SORIN, D. J.; KONIDARIS, G. Robot motion planning on a chip. In: Robotics: Science and Systems. [S.l.: s.n.], 2016. Citado na página 39.
PAN, J.; LAUTERBACH, C.; MANOCHA, D. g-planner: Real-time motion planning and global navigation using gpus. In: Twenty-Fourth AAAI Conference on Artificial Intelligence. [S.l.: s.n.], 2010. Citado na página 39.
PAN, J.; MANOCHA, D. Gpu-based parallel collision detection for fast motion planning. The International Journal of Robotics Research, SAGE Publications Sage UK: London, England,v. 31, n. 2, p. 187–200, 2012. Citado nas páginas 39 e 41.
PAPADIMITRIOU, C. H.; STEIGLITZ, K. Combinatorial optimization: algorithms and complexity. [S.l.]: Courier Corporation, 1998. Citado na página 26.
PEDRONI, V. A. Circuit design with VHDL. [S.l.]: MIT press, 2020. Citado na página 105.
PRASAD, A.; KRISHNAMURTHY, S. K.; KIM, Y. Acceleration of dijkstra’s algorithm on multi-core processors. In: IEEE. 2018 International Conference on Electronics, Information,and Communication (ICEIC). [S.l.], 2018. p. 1–5. Citado nas páginas 42 e 52.
ROBOTICS, P. C. Vision and control: fundamental algorithms in matlab. Springer, p. 251–262,2011. Citado nas páginas 28 e 29.
SAKAMOTO, T.; HARADA, K.; WAN, W. Real-time planning robotic palletizing tasks using reusable roadmaps. Journal of Robotics, Networking and Artificial Life, Atlantis Press, v. 6, n. 4, p. 240–245, 2020. Citado na página 40.
SCHÜTZ, B. Partition-based speed-up of dijkstra’s algorithm. Citeseer, 2005. Citado naspáginas 10, 43, 45, 46 e 52.
SHEN, Z.; WAN, Z.; GU, Y.; SUN, Y. Many sequential iterative algorithms can be parallel and (nearly) work-efficient. p. 273–286, 2022. Citado na página 52.
SIEGWART, R.; NOURBAKHSH, I. R.; SCARAMUZZA, D. Introduction to autonomous mobile robots. [S.l.]: MIT press, 2011. Citado na página 35.
STALLINGS, W. Data and computer communications. [S.l.]: Pearson Education India, 2007.Citado nas páginas 10, 14, 26, 31 e 34.
TARAATE, V. SystemVerilog for Hardware Description: RTL Design and Verification. [S.l.]: Springer Nature, 2020. Citado na página 105. . Digital logic design using verilog. [S.l.]: Springer, 2022. Citado na página 105.
THOUTI, K.; SATHE, S. Performance analysis of single source shortest path algorithm over multiple gpus in a network of workstations using opencl and mpi. International Journal of
Computer Applications, Citeseer, v. 975, p. 8887, 2013. Citado na página 42.
TOMMISKA, M.; SKYTTÄ, J. Dijkstra’s shortest path routing algorithm in reconfigurable hardware. In: SPRINGER. International Conference on Field Programmable Logic and Applications. [S.l.], 2001. p. 653–657. Citado na página 42.
VAIRA, G.; KURASOVA, O. Parallel bidirectional dijkstra’s shortest path algorithm. Databases and Information Systems VI, Frontiers in Artificial Intelligence and Applications, v. 224,2011. Citado nas páginas 14, 46, 47 e 52.
WEISS, M. A. Data structures & algorithm analysis in C++. [S.l.]: Pearson Education, 2012.Citado nas páginas 26, 27 e 31. | pt_BR |